HyperTransport Specifications

The most current HyperTransport technology I/O Link Specification is Release 2.0. To previous specifications, HyperTransport Release 2.0 adds three new speed grades: 2.0 GigaTransfers/second, 2.4 GigaTransfers/second and 2.8 GigaTransfers/second. These new speed grades yield a 16 Gigabyte/second, 19.2 Gigabyte/second and 22.4 Gigabyte/second aggregate bandwidth, an improvement of 75 percent as compared to previous 1.x specifications. In addition, HyperTransport Release 2.0 adds to the existing PCI and PCI-X mapping to include a mapping to PCI Express.

One of the important features of this new specification is that Specification 2.0 devices are fully backward compatible with prior 1.x devices. This means that existing investments in the technology will continue to be leveraged in the future.

These new capabilities make HyperTransport technology the highest performance, lowest latency chip-to-chip I/O link available today and continue the HyperTransport tradition of interoperability with popular industry technologies.

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HyperTransport DirectPacket™ Release 1.10 is backward compatible to previous releases and defines four major features to the HyperTransport 1.x technology specification: native packet handling for efficient transport of user packets through board-level systems, a robust retry protocol for high reliability server and communications systems, peer-to-peer routing for direct connection between I/O devices, and three new sets of Virtual Channels including 16 channels optimized for streaming traffic.

These capabilities make HyperTransport technology the most efficient means to stream packets at the board level. By efficient, we mean that not only does HyperTransport technology exhibit the lowest latency in moving data from point A to point B, but it also requires the least packet overhead when moving 64-byte chunks of data. These new capabilities also make HyperTransport ideal for enhancing performance when linking high speed streaming data technologies such as SPI-4, XAUI, and other communications technologies to board-level systems. These bring communications-oriented packet-handling capabilities to otherwise standard processor-centric computing systems.

The HyperTransport Specification Release 1.05 adds four major features to the 1.03 HyperTransport technology specification: HyperTransport switches, enhanced PCI-X 2.0 interworking, greater transaction concurrency, and 64-bit addressing.

The HyperTransport switch function enables the connection of virtually unlimited numbers of HyperTransport devices. Logically, a switch appears to the system as a tree of PCI-compatible devices and bridges. A given switch can be partitioned to support several separate trees.

The 1.05 enhanced PCI-X 2.0 interworking features simplify the connection of HyperTransport-enabled systems to PCI-X 2.0 subsystems by supporting PCI-X 2.0 error indications and device configuration messages of up to 4K bytes. This supports the 128 byte burst message feature in PCI-X 2.0.

The 1.05 concurrency feature eliminates potential bottlenecks in networking applications by allowing up to 128 outstanding requests.

The HyperTransport Release 1.05 64-bit addressing feature extends the original specification’s 40-bit address in order to support large address spaces needed by some large networking and server applications. The 64-bit command feature is backward compatible with older address schemes, making the 64-bit address optional and enabled on a link-by-link basis.