HyperTransport
interconnect technology is a high-performance,
high-speed, high-bandwidth, point-to-point
link that provides the lowest possible latency for chip-to-chip links. HyperTransport technology provides a
flexible, scalable interconnect architecture designed to reduce the
number of buses within the system, provide a
high-performance link for applications ranging from embedded systems, to personal computers and servers, to network equipment and supercomputers.
HyperTransport technology's aggregrate
bandwidth of 22.4GB/sec represents better than a 70-fold
increase in data throughput over legacy PCI buses. While
providing far greater bandwidth, HyperTransport
technology complements legacy I/O standards like PCI as
well as emerging technologies like PCI-X and PCI Express.
| FEATURES CHART |
| Feature/Function |
HyperTransport Technology |
| Bus Type |
Dual, unidirectional, point-to-point links |
| Link Width |
2, 4, 8, 16, or 32 bits |
| Protocol |
Packet-based, with packets in multiples of four bytes (32 bits) |
Bandwidth
(Each Direction) |
100 MBytes to 11.2 GB/sec. |
| Data Throughput |
Up to 22.4 Gigabytes/sec. |
| Signaling |
1.2-V Low-Voltage Differential Signaling (LVDS) with a 100-ohm differential impedance |
| Multiprocessing Support |
Yes |
| Memory Model |
Coherent and non-coherent |
The HyperTranport Specification is clearly defined
and maintained by the HyperTransport Consortium. The
non-profit consortium publishes the specification,
drives the development of future HyperTransport
specifications and manages all specification issues.
This enables the developer to confidently implement
HyperTransport technology with the assurance that the
resulting system will be interoperable with other
HyperTranport-based subsystems.
Want to Learn More?
MindShare, a member of the HyperTransport Consortium,
offers a comprehensive course that details the
application and operation of HyperTransport Technology.
Go to http://www.mindshare.com/
for more information.
MindShare has also written
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