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HyperTransport™
Consortium and Specifications FAQs
1. Who is the consortium?
The Consortium is a non-profit organization whose membership is
open to any commercial or educational organization. It manages the
HyperTransport Specification and promotes the technology to the
industry at large. Promoter and Contributor members are eligible for
membership in Technical and Marketing Task Force groups that manage
the specification and direct the marketing outreach programs.
2. What are the benefits of joining the consortium?
A primary benefit of membership in the HyperTransport
Consortium is gaining royalty-free use of HyperTransport
technology Intellectual Property.Other important
benefits include early access to technology and
marketing roadmaps, training on an important industry
technology, and the ability (for Promoter and
Contributor members) to participate in defining
future HyperTransport technology/marketing directions.
For more information go to the
membership benefits information page.
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3. What does it cost to join the consortium?
The HyperTransport Consortium is based on five
membership classes: Promoter, Contributor,
Advisor, Adopter, Academic. Major differences
between membership classes are the type of rights and
free services the member is entitled. Adopter
memberships are $5,000 annually, Advisor and
Contributor membership are $15,000 annually, Promoter
memberships are $40,000 annually. Additional membership
class information can be found at the
membership benefits information page.
4. How many members are in the consortium?
There are approximately 40 members in the consortium.
Membership is composed of major industry players in the
personal computer, server, network equipment, silicon
IP, software and supercomputing markets and they have
committed significant resources to developing either
working silicon or test and evaluation systems.
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5. Who are the Founding Members of the Consortium?
Advanced Micro Devices, Alliance Semiconductor, Apple
Computer, Broadcom Corporation, Cisco Systems, NVIDIA,
PMC-Sierra, Sun Microsystems, and Transmeta.
6. What is the current specification release?
The most current HyperTransport technology I/O Link
Specification is Release 2.0. HyperTransport Release 2.0
boosts the top speed to 2.8 GigaTransfers/second, yielding a
22.4 Gigabyte/second aggregate bandwidth. In addition,
HyperTransport Release 2.0 adds to the existing PCI and PCI-X
mapping to include a mapping to PCI Express.
HyperTransport Technology FAQs
7. What is HyperTransport technology?
HyperTransport chip-to-chip interconnect technology is a
highly optimized, high performance and low latency
board-level architecture for embedded and open-
architecture systems. It provides up to 22.4
Gigabyte/second aggregate CPU to I/O or CPU to CPU
bandwidth in a highly efficient chip-to-chip technology
that replaces existing complex multi-level buses. In
addition to delivering the industry's highest bandwidth,
frequency scalability, and lowest implementation cost,
the technology is software compatible with legacy
Peripheral Component Interconnect (PCI) and PCI-X and
emerging PCI Express technologies. HyperTransport
technology delivers state-of the-art bandwidth by means
of easy-to-implement Low Voltage Differential Signaling
(LVDS) point-to-point links, delivering increased data
throughput while minimizing signal crosstalk and EMI. It
employs a packet-based data protocol to eliminate many
sideband (control and command) signals and supports
asymmetric, variable width data paths.
8. What are the key characteristics of HyperTransport technology?
Key characteristics of the royalty-free HyperTransport
technology include low latency, high bandwidth, excellent
scalability, high integration, low power consumption, PCI
software transparency, and small PCB footprint, with PCB
manufacturing friendly electrical implementation.
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9. How does HyperTransport technology compare to other bus
technologies?
As compared to older multidrop, shared buses such as PCI,
PCI-X or SysAD, HyperTransport provides a far simplier
electrical interface, but with much greater bandwidth.
Instead of a wide, address/data/control multidrop,
shared bus such as implemented by PCI, PCI-X or SysAD
technologies, HyperTransport deploys narrow, but very
fast unidirectional links to carry both data and command
information encoded into packets. Unidirectional links
provide significantly better signal integrity at high
speeds and enable much faster data transfers with
low-power 1.2V LVDS signals. In addition, link widths
can be asymmetrical, meaning that 2 bit wide links can
easily connect to 8 bit wide links and 8 bit wide links
can connect to 16 or 32 bit wide links and so on. Thus,
the HyperTransport Technology eliminates the problems
associated with high speed parallel buses with their
many noisy bus signals (multiplexed data/address, and
clock and control signals) while providing scalable
bandwidth wherever it is needed in the system. As
compared to newer serial I/O technologies such as
RapidIO and PCI Express, HyperTransport shares some raw
bandwidth characteristics, but is significantly
different in some key characteristics. HyperTransport
was designed to support both CPU-to-CPU communications
as well as CPU-to-I/O transfers, thus, it features very
low latency. Consequently, it has been incorporated into
multiple x86 and MIPS architecture processors as an
integrated front-side bus. Serial technologies such as
PCI Express and RapidIO require serial-deserializer
interfaces and have the burden of extensive overhead in
encoding parallel data into serial data, embedding clock
information, re-acquiring and decoding the data stream.
The parallel technology of HyperTransport needs no
serdes and clock encoding overhead making it far more
efficient in data transfers.
10. How does HyperTransport technology performance compare to other
bus technologies?
Performance comparisons between technologies can be
problematical. Raw clock and data transfer speeds do not
take into account raw bandwidth and "true" bandwidth (total
data transfer minus overhead). PCI and PCI-X buses lag far
behind any of the other newer technologies. For example, the
traditional 32-bit/33MHz PCI bus transfers data at 133
Megabytes per second, while PCI-X transfers data at up to 1
gigabytes per second. RapidIO defines a data rate of 3.125
gigabit/second, while PCI Express defines a 2.5
gigabit/second data rate. The latest 2.0 HyperTransport
specification defines a 2.8 gigatransfers/second data rate.
However, gross bandwidth figures are less important than the
net bandwidth available for data transfers. HyperTransport
delivers 22.4 gigabytes/second of aggregate bandwidth with
the lowest latency and least clocking overhead. This yields
a bandwidth approximately 80 times faster than traditional
PCI buses.
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11. Why is HyperTransport technology so inexpensive to implement?
There are several factors that make implementing
HyperTransport less expensive than other alternatives.
One is that it is a royalty-free (to consortium
members)technology. This means that each system shipped
using HyperTransport technology is free of any royalty
payment. Another is the nature of the electrical
protocols. Using enhanced 1.2 volt LVDS signaling
reduces signal noise, using non-multiplexed lines
cuts down on signal activity and using dual-data rate
clocks lowers clock rates while increasing data
throughput. All of these elements simplify manufacturing
costs and makes HyperTransport 4-layer PCB manufacturing
process friendly. Since HyperTransport also eliminates
many sideband signals required by other technologies, it
eliminating many signal traces and reduces board real
estate. New specifications are backward compatible with
previous generations of specification, extending the
investment made in one generation of
HyperTransport-enabled device to future generations.
Finally, HyperTransport devices are PCI software
compatible, thus they require little or no software
overhead
12. What are HyperTransport hosts, caves, tunnels, and bridges?
Each HyperTransport link must have at least two ends, a host
that is the source of HyperTransport information and signals and an
endpoint or cave. If additional HyperTransport devices need to be
added to a link, a tunnel is used to connect additional HyperTransport devices to the link. If a HyperTransport link is
expanded to connect to another I/O technology, a bridge links the
HyperTransport link to the other I/O technology. An example would be
a PCI-to-HyperTransport bridge device. Tunnels and bridges can serve
as endpoints or caves.
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13. What is a HyperTransport switch?
The HyperTransport Specification Release 1.05 defines
switch characteristics. A HyperTransport I/O
switch can handle multiple HyperTransport I/O data
streams and manage the interconnection between attached
HyperTransport I/O devices. A four-port HyperTransport
switch could aggregate data from multiple downstream
ports into a single high speed uplink, or it can route
port-to port connections.
14. At what clock speeds does HyperTransport technology operate?
HyperTransport technology devices are designed to operate
at multiple clock speeds from 200MHz up to 1.4 GHz, and
utilize double data rate technology transferring two
bits of data per clock cycle, for an effective transfer
rate of up to 2.8 gigatransfer/sec in each direction.
Since transfers can occur in both directions
simultaneously, an aggregate transfer rate of 11.2
gigabytes per second in a 16 bit HyperTransport I/O Link
and an aggregate transfer rate of 22.4 gigabytes per
second in a 32-bit HyperTransport I/O Link can be
achieved. To allow for system design optimization, the
clocks of the receive and transmit links may beset at
different rates.
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15. What is the width of the HyperTransport I/O link bus?
The HyperTransport I/O Link is designed to allow very flexible
implementations, allowing data widths of 2, 4, 8, 16, or 32-bits in
each direction. Devices negotiate the bus width during initialization
and operate accordingly thereafter. To allow for system design
optimization, the clocks of the receiving and transmitting links may
be set at different rates.
16. With what buses and I/O technologies is HyperTransport technology
compatible?
HyperTransport technology is completely software
compatible with PCI and PCI legacy I/O extensions such
as PCI-X 1.0 and 2.0. Specification 2.0 includes mapping
to PCI Express protocols. In addition, because of its
bandwidth and packetized data/command protocol, it is
easily integrated using HyperTransport bridge devices to
any of today's advanced I/O technologies, such as AGP
8x, Firewire, USB, InfiniBand, PL-3, SPI-4.2, SPI-5.0,
and gigabit Ethernet.
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17. Why is HyperTransport technology compared to PCI technology?
PCI is the most pervasive bus in personal computing and is
widely used in networking applications, servers and even
in embedded systems. HyperTransport technology preserves
the large investment that has already been made in PCI
while providing a powerful combination of low-cost
implementations and high bandwidth. HyperTransport
solves many of the technical limitations of PCI while
preserving the software infrastructure of this widely
used technology.
18. Is HyperTransport technology Plug & Play compatible?
Yes. HyperTransport I/O devices are designed to use the standard
Plug 'n Play methodology and boot, run, and driver compatible with
any standard PCI compliant operating system.
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19. How can I get HyperTransport technology training?
MindShare, one of the leading technical training companies
in the hardware industry, offers a HyperTransport course
that is a comprehensive guide to HyperTransport
technology. It details all facets of HyperTransport
technology including the protocol, electrical
environment, error detection and reporting, and
configuration. The course also provides the necessary
background for understanding the performance
considerations when designing HyperTransport systems. As
part of the benefits of being a HyperTransport
Consortium member, you may participate in a free
MindShare HyperTransport training course. For more
information please
click here. In addition, MindShare offers a
detailed
HyperTransport System Architecture book.
HyperTransport-enabled Products FAQs
20. What HyperTransport-enabled products are available?
The HyperTransport-enabled product portfolio includes
bridge, chipset and graphic chips from AMD, ALi,
Alliance Semiconductor, NVIDIA, PLX Technology, and VIA
Technologies; programmable-logic devices from Altera and
Xilinx; processors and security processors from AMD,
Broadcom, Hifn, PMC-Sierra, and Transmeta; IP cores from
Altera, Artisan/ARM, GDA Technologies, and Xilinx; BIOS
software from AMI; verification and test tools from
Agilent, FuturePlus, GDA Technologies, and Teradyne; and
training courses and an architecture reference manual
from Mindshare. A full product listing can be found
at::
http://www.hypertransport.org/products/index.cfm
21. What applications use HyperTransport technology?
HyperTransport is used in a wide range of high-volume and
high-performance applications from high-performance, low
cost consumer products all the way to supercomputers.
Key HyperTransport-enabled products included consumer
products, desktop and mobile personal computers,
servers, network equipment, embedded applications,
communications equipment and supercomputers
22. How many HyperTransport-enabled devices are shipping in volume?
Specific company shipments are proprietary, but the
most recent IDC market study estimated that there were over
38 million HyperTransport ports shipped in 2003, with
shipments expected to climb to over 200 million by 2006.
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