HyperTransport in High Performance PCs and Workstations
HyperTransport Enables the Future in PC and Workstation Platforms
The move in PCs is to faster processors with higher clock speeds,
blazing fast dual data rate (DDR) memories, a requirement to support
legacy I/O devices and, of course, the need to respond the market's move
to lower costs and system prices. As CPUs blaze past previous
untouchable GHz milestones and new memories make possible mega-data
transfers, it is clear that system design must approach old problems in
a new way - especially if cost and space constraints are to be met.
In the PC, the chipset SouthBridge defines the I/O of the system and
it is clear what the trends are: I/O is moving from parallel to high speed serial to achieve the
benefits of lower pin counts, lower real estate costs and to lower
system cost while improving performance. Proven legacy technologies
such as PCI, ATA, and SCSI are being supplemented by USB, Firewire,
and serial ATA technologies. HyperTransport technology plays a
pivotal role by integrating these new faster technologies into a manageable I/O stream and linking to legacy PCI and PCI-X buses.
HyperTransport even supports emerging I/O technologies like PCI
Express. As shown in the diagram above, the SouthBridge can
use the high speed HyperTransport bus to connect slower peripherals and
legacy subsystems such as PCI and PCI-X to the higher speed processor
and DDR memories. In systems with processors that integrate
HyperTransport links on-board, HyperTransport can be used as a fast
front-side bus, eliminating the NorthBridge entirely.
In the PC space, HyperTransport is a key technology because it not
only offers far greater on-board, chip-to-chip I/O bandwidth, but it
also can be easily integrated into legacy PCI and PCI-X I/O systems.
Interoperability with PCI Express technology ensures that future
systems can deploy HyperTransport technology to boost performance of
PCI Express-based I/O systems.
HyperTransport advantages such as low latency with no data-encoding,
coherency option for easy processor-to-processor communications,
scalable bandwidth through implementation of asymmetrical bus-widths of
2, 4, 8, 16, or 32 bits wide each and simple differential I/O signaling
with no clock recovery overhead make it idea for the higher performance,
low cost system platforms for the future highend personal computer
system.
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